Clock generation circuits can be used to clock synchronous digital circuits and mixed-signal, such as analog-to-digital converters. A clock generation circuit provides one or more repetitive clock signals, each having a constant period. A typical clock signal has a first phase and a second phase within a single period of the clock signal. Typically, a clock generation circuit provides both an inverted clock signal and a non-inverted clock signal. In addition, a clock generation circuit may be designed to generate a delayed clock signal that is based upon another clock signal generated by the circuit.
Two clock signals can be timed such that they are non-overlapping with respect to each other. Two clock signals are non-overlapping if only one of the clock signals can be high (or low) at any given time. In other words, if two non-overlapping clock signals are viewed on the same time axis, the respective clock pulses will never overlap and will always be separated from each other. A simple non-overlapping clock generation circuit may provide a non-inverted clock signal and inverted clock signal that respectively transition (at the trailing end) before a delayed non-inverted clock signal and a delayed inverted clock signal.
Conventional non-overlapping clock generator circuits are well known in the art and are commonly used to generate the required non-overlapping clock signals for switched capacitor circuits. In general, non-overlapping clock signals are used to reduce voltage error in such switched capacitor circuits. However, as the signal frequencies to be processed and the associated clock frequencies increase, conventional non-overlapping clock generator circuits use an unacceptably large portion of the clock period to generate the non-overlapped clock signals and become the limiting factor in operating switched capacitor circuits at high clock frequencies.
A pipelined analog-to-digital converter is one practical application for a non-overlapping clock generator. A pipelined analog-to-digital converter typically utilizes multiple analog-to-digital stages coupled in series, where each stage may be driven by different derivative clock signals based upon a “primary” clock signal and its inverted or complementary clock signal. One conventional approach for the generation of these derivative clock signals relies on a single clock generator circuit that generates all of the clock signal variants. A single clock generator circuit, however, must be designed to meet the requirements of the quickest and most accurate stage while driving the load from all stages. Consequently, such a single clock generator circuit may be over-designed, excessively complex, and require an impractical amount of physical space and operating power. In addition, a single clock generator circuit may need to provide very large charging currents for short periods of time, and such currents can interact with the package and bond wire inductances (causing the power supply voltages to bounce in an undesirable manner).
Another conventional approach uses a “local” clock generator circuit for each stage in the pipelined analog-to-digital converter, where each clock generator circuit is optimized for the specific loading and timing requirements of the respective converter stage, thereby saving power and area relative to a single clock generator circuit implementation. However, in addition to the clock synchronization requirements for each individual stage, essentially the same stringent timing relationships between the clock phases of a stage and the stage that follows it in the pipeline are required in order to process an input signal correctly through each stage of the pipeline. Since “local” per-stage clock generators cannot be readily synchronized globally with respect to the other local clock generators throughout the pipeline, this approach does not adequately enable precision analog-to-digital converter performance.
Accordingly, it is desirable to have a non-overlapping clock generator that can provide a variety of clock signals having specific timing relationships relative to one another in an efficient and robust manner. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.